On-Chip Implementation of High Speed and High Resolution Pipeline Radix 2 FFT

IEEE International Conference on Intelligent and Advanced System ICIAS 2007. University Technology Petronas, Malaysia. ISBN: 978-1-4244-1355-3 pp. 1286 – 1288

3 Pages Posted: 16 Jul 2012 Last revised: 17 Jul 2012

See all articles by Rozita Teymourzadeh

Rozita Teymourzadeh

Neonode Inc

N. Mahdavi

affiliation not provided to SSRN

Masuri Bin Othman

affiliation not provided to SSRN

Date Written: July 15, 2012

Abstract

A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log(2) N)11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.

JEL Classification: F14, L, O14

Suggested Citation

Teymourzadeh, Rozita and Mahdavi, N. and Bin Othman, Masuri, On-Chip Implementation of High Speed and High Resolution Pipeline Radix 2 FFT (July 15, 2012). IEEE International Conference on Intelligent and Advanced System ICIAS 2007. University Technology Petronas, Malaysia. ISBN: 978-1-4244-1355-3 pp. 1286 – 1288, Available at SSRN: https://ssrn.com/abstract=2107252

Rozita Teymourzadeh (Contact Author)

Neonode Inc ( email )

2880 Zanker Rd
Suite 362
San Jose, CA San Jose 95134
United States

HOME PAGE: http://www.rozitateymourzadeh.com/

N. Mahdavi

affiliation not provided to SSRN

Masuri Bin Othman

affiliation not provided to SSRN

Do you have negative results from your research you’d like to share?

Paper statistics

Downloads
45
Abstract Views
406
PlumX Metrics