FPGA Implementation of Pipeline Digit-Slicing Multiplier-Less Radix 2 Power of 2 DIF SDF Butterfly for Fast Fourier Transform Structure

European Conference on Antennas and Propagation (EUCAP2011). Pp. 4168-4172.

5 Pages Posted: 27 Apr 2018

See all articles by Yazan Samir Algnabi

Yazan Samir Algnabi

National University of Malaysia (UKM) - Institute of Microengineering & Nanoelectronics (IMEN)

Rozita Teymourzadeh

Neonode Inc

Masuri Othman

National University of Malaysia (UKM) - Institute of Microengineering & Nanoelectronics (IMEN)

Md Shabiul Islam

National University of Malaysia (UKM) - Institute of Microengineering & Nanoelectronics (IMEN)

Date Written: 2011

Abstract

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach is taken; in order to reduce computation complexity in butterfly multiplier, the digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 22 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.

Keywords: Pipelined digit-slicing multiplier-less, Fast Fourier Transform (FFT), Verilog HDL, Xilinx, Radix 22 DIF SDF FFT

JEL Classification: F14, L, O14, C63

Suggested Citation

Algnabi, Yazan Samir and Teymourzadeh, Rozita and Othman, Masuri and Islam, Md Shabiul, FPGA Implementation of Pipeline Digit-Slicing Multiplier-Less Radix 2 Power of 2 DIF SDF Butterfly for Fast Fourier Transform Structure (2011). European Conference on Antennas and Propagation (EUCAP2011). Pp. 4168-4172. , Available at SSRN: https://ssrn.com/abstract=3158658

Yazan Samir Algnabi

National University of Malaysia (UKM) - Institute of Microengineering & Nanoelectronics (IMEN)

43600 Bandar Baru Bangi
Bangi, Selangor 06010
Malaysia

Rozita Teymourzadeh (Contact Author)

Neonode Inc ( email )

2880 Zanker Rd
Suite 362
San Jose, CA San Jose 95134
United States

HOME PAGE: http://www.rozitateymourzadeh.com/

Masuri Othman

National University of Malaysia (UKM) - Institute of Microengineering & Nanoelectronics (IMEN)

43600 Bandar Baru Bangi
Bangi, Selangor 06010
Malaysia

Md Shabiul Islam

National University of Malaysia (UKM) - Institute of Microengineering & Nanoelectronics (IMEN)

43600 Bandar Baru Bangi
Bangi, Selangor 06010
Malaysia

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