Two Stage CMOS Operational Amplifier: Analysis and Design

Mody University International Journal of Computing and Engineering Research 3 (1), 2019, 40-44

5 Pages Posted: 9 Aug 2019

Date Written: August 6, 2019

Abstract

This paper describes analysis and design of 2-stage CMOS operational amplifier (Op Amp). The designed circuit operates at 3.3 V of supply voltage and at tsmc 0.35 μm CMOS technology. The performance parameters such as: gain, phase margin, GBW, ICMR, Slew Rate, Offset, CMRR, output swing etc. also have been analyzed after simulation which is carried out using Cadence Virtuoso Tool. The OpAmp is designed to display a unity gain frequency of 7.85 MHz and exhibits a gain of 86.23 dB with a 49° phase margin. Obtained results also agree with theoretical predictions.

Keywords: Scaling and differential amplifier, Stability, Two stage operational amplifier

Suggested Citation

suman, shruti, Two Stage CMOS Operational Amplifier: Analysis and Design (August 6, 2019). Mody University International Journal of Computing and Engineering Research 3 (1), 2019, 40-44, Available at SSRN: https://ssrn.com/abstract=3433181 or http://dx.doi.org/10.2139/ssrn.3433181

Shruti Suman (Contact Author)

K L University ( email )

GREENFIELDS,
VADDESWARAM
GUNTUR, IN 522502

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