A DFT Tactic Aimed At Testable Q-Flop Rudiments

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, 2019

Posted: 3 Jun 2020

See all articles by NAGARAJAN N R

NAGARAJAN N R

K. RAMAKRISHNAN COLLEGE OF ENGINEERING

Date Written: APRIL 5, 2019

Abstract

In the field of VLSI Design the flip flop elements play an important role in terms of memory management. For registers and memory elements in all the designs either Q flip flop or the D flip flop has its major dominance. Especially the Q-Flop is an alternative memory component for designs that are susceptible to to metastability. This has been noticeably reconnoitered by the former investigation efforts, principally in the schemes of synchronization. But the testing methodologies for these Q flop elements are rarely found and has only few number of support of the insertion of test elements along with it because of its complexity and its perilous nature. The proposed Q flop elements integrate itself to a standard synthesis and scans with automation providing automation solutions in real time. The technique which is built in for testing is one of the approach of DfT. The test results proves the trade offs between the power, area and speed. The circuit design is done using Tanner EDA for computing the design and its code is synthesized for its ability check in Xilinx. The power analysis and area analysis proved to be remarkably better for an automation testing of Q flop elements.

Keywords: Q Flop, RTL, FIFO, LSSD, DfT, Metastability

JEL Classification: C67

Suggested Citation

N R, NAGARAJAN, A DFT Tactic Aimed At Testable Q-Flop Rudiments (APRIL 5, 2019). International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, 2019, Available at SSRN: https://ssrn.com/abstract=3593281

NAGARAJAN N R (Contact Author)

K. RAMAKRISHNAN COLLEGE OF ENGINEERING ( email )

SAMAYAPURAM
TIRUCHY
TIRUCHY, TN Tamil Nadu 621112
India

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